This invention relates to a one mask technique and the resulting structure for making a substrate contact from the top surface of an integrated circuit device. The technique is particularly useful for bipolar integrated circuit structures wherein buried collectors are normally formed in a maskless, blanket fashion and devices subsequently isolated through one of the deep-isolation techniques.
In bipolar integrated circuits, a low-resistance path to bias the substrate is normally required. Further, in the case of certain types of chip packaging, the substrate biasing contact location must be situated at the top surface of the chip.
Normally, in the case of integrated circuits involving deep-dielectric isolation walls, the method to realize top substrate contact would involve employing one masking step to pattern the buried collectors and at least one more masking step to achieve a low-resistance access to the substrate. This invention provides top substrate contacting by using only one masking step to pattern the buried collectors and also simultaneously achieve a low-resistance access to the substrate.
As stated in the foregoing, the technique of this invention has particular applicability to integrated circuits involving deep dielectric isolation. However, the technique is also directly applicable in the case of integrated circuits which involve conventional isolation methods, i.e, those incorporating exclusively PN junction isolation or partial PN junction isolation in conjunction with recessed oxide isolation. In integrated circuits involving one of these conventional isolation schemes, the application of this invention would normally be restricted to the cases where the doping of the buried collectors is moderate so that the collector-substrate capacitance would not be excessive.
Prior art techniques of forming substrate contacts, that have been evaluated vis-a-vis this invention are U.S. Pat. Nos. 3,817,750; 4,196,228; 4,256,514; and 4,309,812. None are considered to be relevant to this invention.